1. Field of the Invention
This invention relates to integrated circuits (IC's), and more particularly, to controlling access to various portions of an IC using design-for-test (DFT) features in an IC.
2. Description of the Related Art
Integrated circuits (IC's) have become increasingly complex as the technology for their design and manufacture has advanced. Due to the increased complexity of IC's, testing to detect manufacturing and design defects has correspondingly increased in importance. However, the increase complexity of modern IC's may make access to certain portions of an IC difficult, if not impossible. Furthermore, some portions (e.g., secure storage, cryptography circuits, etc.) of certain IC's may be designed to be inaccessible from external pins and/or various other functional units.
To overcome the problem of providing full access to the various circuits and functional units of an IC, various design for test (DFT) techniques have been developed. One such technique is to use built-in self-test (BIST) circuitry, in which tests of various circuits may be conducted without outside intervention.
Another technique that may be used is to provide internal scan chains, or using internal scan chains. Each scan chain may include a number of serially coupled scan elements in which test stimulus data may be input into an IC. Tests of the circuitry within the IC may be conducted based on the test stimulus data. After conducting a test using the stimulus data, test result data may be captured in the scan elements and shifted from the IC for further analysis. Using scan chains and other similar techniques may enable access to and testing of portions of an IC that are otherwise inaccessible, including secure circuits not otherwise intended to be accessible through external pins of the IC.